Category:Digital electronics

C

• ► Digital circuits‎ (5 C, 43 P)
• ► Clock signal‎ (26 P)
• ► Computer hardware‎ (18 C, 26 P)

E

• ► Electronic design automation‎ (14 C, 91 P)

F

• ► Finite automata‎ (47 P)

I

• ► Integrated circuits‎ (19 C, 162 P)

L

• ► Logic design‎ (7 P)
• ► Logic families‎ (39 P)

P

• ► Pinball electronics‎ (1 C, 1 P)

• Digital electronics

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• Portal:Digital electronics

0–9

• List of 4000-series integrated circuits
• 4000-series integrated circuits
• List of 7400-series integrated circuits
• 7400-series integrated circuits

A

• Additron tube
• Adiabatic circuit
• Analog-to-digital timeline
• Antifuse
• Antistatic bag
• Antistatic device
• Asymmetric C-element
• Asynchronous serial communication

B

• Behavior tree (artificial intelligence, robotics and control)
• Beyond CMOS
• Bistability
• Bit slicing
• Bus (computing)
• Bus analyzer
• Bus encoding

C

• C-element
• C166 family
• Channel router
• Charge sharing
• CHMOS
• CMOS
• Combinational logic
• Common Electrical I/O
• Computer hardware
• Computron tube
• Control unit

D

• Data storage tag
• Databending
• Josephson junction count
• Degradation (telecommunications)
• Delay line memory
• Delay-insensitive minterm synthesis
• Delay-locked loop
• Design flow (EDA)
• Design for additive manufacturing
• Design for manufacturability
• Digital clock manager
• Digital feedback reduction
• Digital lollipop
• Digital signal conditioning
• Digital signal processing
• Direct-coupled transistor logic
• Double data rate
• Dye-and-pry

E

• Early completion
• IBM Elastic Interface
• Electrostatic discharge materials
• Encoder (digital)
• Europe Card Bus

F

• Fault model
• Field-programmability
• Finite state machine with datapath
• Flip-flop (electronics)
• Frequency counter
• Front Panel Data Port
• FT32
• Fuzzy electronics

G

• Glitch
• Glitch art
• Glitch removal
• Glitching

H

• Hazard (logic)
• HCMOS
• High-speed transceiver logic

I

• In-system programming
• Ingress cancellation
• Integrated circuit
• Interconnect bottleneck

J

• Jitterlyzer

L

• Leading zero
• Level shifter
• LiquidHD
• List of Wi-Fi microcontrollers
• Logic analyzer
• Logic level
• Logic optimization
• Logic probe
• Logic redundancy
• Logic synthesis
• Logical effort
• Low Power Flip-Flop Techniques

M

• Media processor
• Memory cell (computing)
• Message Signaled Interrupts
• Metastability (electronics)
• Microprocessor
• Microprocessor chronology
• ModelSim
• Multi-channel length
• Multi-threshold CMOS
• Multiple-emitter transistor
• MVCML

N

• Nanoroute
• NORBIT
• NT (cassette)
• Numerically controlled oscillator

O

• One-cold
• One-hot
• Oversampled binary image sensor

P

• Parametron
• PCMOS
• PLEDM
• Postdigital
• Posted write
• Power gating
• Power network design (IC)
• Power optimization (EDA)
• Power–delay product
• Programmable interrupt controller
• Programmable interval timer
• Propagation delay
• Propagation time

Q

• Quad data rate
• Quantum flux parametron

R

• Rapid single flux quantum
• Reconfigurable computing
• Register file
• Reversible computing
• Runt pulse

S

• Schmitt trigger
• SCMOS
• Self-clocking signal
• Semiconductor memory
• Sequential logic
• SerDes
• Serial FPDP
• Shift register lookup table
• Signal edge
• Signal integrity
• Simatic S5 PLC
• Single event upset
• Slave clock
• Soft error
• Static discipline
• STEbus
• Stuck-at fault
• Superconducting computing
• Switching circuit theory

T

• Three-state logic
• Time-slot interchange
• Transistor fault
• Transistor–transistor logic
• Triggering device

U

• UML state machine

V

• Virtus (chipset)
• Voltage regulator module

X

• Xilinx ISE
• Xilinx Vivado